How innovations create international markets : Three case studies on Finnish high-tech development and commercialization projects

Siirretty Doriast

Mixed-mode cellular array processor realization for analyzing brain electrical activity in epilepsy

This thesis deals with the realization of hardware that is capable of computing algorithms that can be described using the theory of polynomial cellular neural/nonlinear networks (CNNs). The goal is to meet the requirements of an algorithm for predicting the onset of an epileptic seizure. The analysis associated with this application requires extensive computation of data that consists of segments of brain electrical activity. Different types of computer architectures are overviewed. Since the algorithm requires operations in which data is manipulated locally, special emphasis is put on assessing different parallel architectures. An array computer is potentially able to perform local computational tasks effectively and rapidly. Based on the requirements of the algorithm, a mixed-mode CNN is proposed. A mixed-mode CNN combines analog and digital processing so that the couplings and the polynomial terms are implemented with analog blocks, whereas the integrator is digital. A/D and D/A converters are used to interface between the analog blocks and the integrator. Based on the mixed-mode CNN architecture a cellular array processor is realized. In the realized array processor the processing units are coupled with programmable polynomial (linear, quadratic and cubic) first neighborhood feedback terms. A 10 mm2, 1.027 million transistor cellular array processor, with 2×72 processing units and 36 layers of memory in each is manufactured using a 0.25 μm digital CMOS process. The array processor can perform gray-scale Heun's integration of spatial convolutions with linear, quadratic and cubic activation functions for 72×72 data while keeping all I/O operations during processing local. One complete Heun's iteration round takes 166.4 μs, while the power consumption during processing is 192 mW. Experimental results of statistical variations in the multipliers and polynomial circuits are shown. Descriptions regarding improvements in the design are also explained. The results of this thesis can be used to assess the suitability of the mixed-mode approach for implementing an implantable system for predicting epileptic seizures. The results can also be used to assess the suitability of the approach for implementing other applications.reviewe

Large-scale memristive associative memories

Associative memories, in contrast to conventional address-based memories, are inherently fault-tolerant and allow retrieval of data based on partial search information. This paper considers the possibility of implementing large-scale associative memories through memristive devices jointly with CMOS circuitry. An advantage of a memristive associative memory is that the memory elements are located physically above the CMOS layer, which yields more die area for the processing elements realized in CMOS. This allows for high-capacity memories even while using an older CMOS technology, as the capacity of the memory depends more on the feature size of the memristive crossbar than on that of the CMOS components. In this paper, we propose the memristive implementations, and present simulations and error analysis of the autoassociative content-addressable memory, the Willshaw memory, and the sparse distributed memory. Furthermore, we present a CMOS cell that can be used to implement the proposed memory architectures.</div

Improving efficiency of the sample design in the Finnish horticultural survey

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Improving efficiency of the sample design and reducing survey costs in the Finnish horticultural survey

Esitelmä201

Memristive Circuits for LDPC Decoding

We present design principles for implementing decoders for low-density parity check codes in CMOL-type memristive circuits. The programmable nonvolatile connectivity enabled by the nanowire arrays in such circuits is used to map the parity check matrix of an LDPC code in the decoder, while decoding operations are realized by a cellular CMOS circuit structure. We perform detailed performance analysis and circuit simulations of example decoders, and estimate how CMOL and memristor characteristics such as the memristor OFF/ON resistance ratio, nanowire resistance, and the total capacitance of the nanowire array affect decoder specification and performance. We also analyze how variation in circuit characteristics and persistent device defects affect the decoders.</div

Synthesis report on utilization of peatland forests for biomass production

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Drainage and Stand Growth Response in Peatland Forests—Description, Testing, and Application of Mechanistic Peatland Simulator SUSI

Drainage is an essential prerequisite in peatland forest management, which generally, but not always, increases stand growth. Growth response depends on weather conditions, stand and site characteristics, management and biogeochemical processes. We constructed a SUSI-simulator (SUoSImulaattori, in Finnish), which describes hydrology, stand growth and nutrient availability under different management, site types and weather conditions. In the model development and sensitivity analysis, we used water table (WT) and stand growth data from 11 Scots pine stands. The simulator was validated against a larger dataset collected from boreal drained peatlands in Finland. In validation, SUSI was shown to predict WT and stand growth well. Stand growth was mainly limited by inadequate potassium supply, and in Sphagnum peats by low oxygen availability. Model application was demonstrated for ditch network maintenance (DNM) by comparing stand growth with shallow (−0.3 m) and deep ditches (−0.9 m): The growth responses varied between 0.5 and 3.5 m3 ha−1 in five years, which is comparable to experimental results. SUSI can promote sustainable peatland management and help in avoiding unnecessary drainage operations and associated environmental effects, such as increased carbon emissions, peat subsidence, and nutrient leaching. The source code is publicly available, and the modular structure allows model extension to cost–benefit analyses and nutrient export to water courses

Drainage and Stand Growth Response in Peatland Forests—Description, Testing, and Application of Mechanistic Peatland Simulator SUSI

Drainage is an essential prerequisite in peatland forest management, which generally, but not always, increases stand growth. Growth response depends on weather conditions, stand and site characteristics, management and biogeochemical processes. We constructed a SUSI-simulator (SUoSImulaattori, in Finnish), which describes hydrology, stand growth and nutrient availability under different management, site types and weather conditions. In the model development and sensitivity analysis, we used water table (WT) and stand growth data from 11 Scots pine stands. The simulator was validated against a larger dataset collected from boreal drained peatlands in Finland. In validation, SUSI was shown to predict WT and stand growth well. Stand growth was mainly limited by inadequate potassium supply, and in Sphagnum peats by low oxygen availability. Model application was demonstrated for ditch network maintenance (DNM) by comparing stand growth with shallow (−0.3 m) and deep ditches (−0.9 m): The growth responses varied between 0.5 and 3.5 m3 ha−1 in five years, which is comparable to experimental results. SUSI can promote sustainable peatland management and help in avoiding unnecessary drainage operations and associated environmental effects, such as increased carbon emissions, peat subsidence, and nutrient leaching. The source code is publicly available, and the modular structure allows model extension to cost–benefit analyses and nutrient export to water courses